1. Field of the Invention
This application relates to Semiconductor memory devices, and more particularly, to a circuit and method of generating a high voltage for a programming operation of flash memory devices.
2. Description of the Related Art
With the development of digital information communication networks, Such as the Internet, used by devices Such as personal digital assistants and cellular phones, nonvolatile memory devices are useful as memory devices capable of Storing information of a mobile terminal in a nonvolatile manner. The nonvolatile memory device includes a flash memory that can electrically erase Stored data and electrically write data.
The flash memory includes Sectors, each including memory cells. The flash memory erases memory cell data block by block (Sector by Sector) and programs data in every memory cell. A NAND type flash memory is increasingly used because its integration and memory capacity is comparable to a dynamic RAM. The NAND type flash memory is constructed Such that memory Strings each include Serially connected memory cells. The memory cells are Serially connected between bit lines and Source lines. The memory Strings are arranged to construct a memory cell array.
FIG. 1 is a block diagram of a conventional flash memory device 100. Referring to FIG. 1, the flash memory device 100 includes a unit block memory cell array 110, a wordline decoder 120, and a high voltage generator 130. The flash memory device 100 may include Several unit block memory cell arrays 110. Wordline decoders are arranged corresponding to each unit block memory cell array 110. For convenience of explanation, FIG. 1 illustrates a Single wordline decoder 120 corresponding to the unit block memory cell array 110.
The block memory cell array 110 includes memory Strings CS connected to n bit lines BL0, BL1, . . . , BLn−1. The memory Strings CS are commonly connected to a Source line CSL. The gates of memory cells M0 through M15 of the memory Strings CS are connected to worldliness WL0 through WL15. The gates of String Select transistors SST respectively connecting the memory Strings CS to the bit lines BL0, BL1, . . . , BLn−1 are connected to a String Select line SSL. The gates of ground Select transistors GST connecting the memory Strings CS to the common Source line CSL are connected to a ground Select line GSL.
The wordline decoder 120 Selectively activates the String Select line SSL, ground Select line GSL and worldliness WL0 through WL15 of the memory cell array 110. The wordline decoder 120 includes a decoder 122 and a wordline driver 124. The decoder 122 receives address Signals ADDR to generate wordline driving Signals S0 through S15, a String Select voltage VSSL and a ground Select voltage VGSL. The wordline driver 124 respectively transfers the wordline driving Signals S0 through S15, String Select voltage VSSL and ground Select voltage VGSL to the worldliness WL0 through WL15, String Select line SSL and ground Select line GSL.
The decoder 122 decodes the received address Signals ADDR to provide corresponding driving voltages, for example, a program voltage Vpgm, an erase voltage Verase, a read voltage Vread or a pass voltage Vpass, to the String Select line SSL, wordlineS WL0 through WL15 and ground Select line GSL in a programming operation, an eraSe operation or a read operation.
The wordline driver 124 includeS high-voltage pass tranSiStorS SN, WN0 through WN15, GN and CN reSpectively connected between the String Select voltage VSSL, the wordline driving SignalS S0 through S15, the ground Select voltage VGSL, and a common Source line voltage VCSL and the String Select line SSL, the wordlineS WL0 through WL15, the ground Select line GSL, and the common Source line CSL. A block wordline BLKWL to which the gateS of the high-voltage pass tranSiStorS SN, WN0 through WN15, GN and CN are connected iS provided with a high voltage VPP generated by the high voltage generator 130.
The high voltage generator 130 generateS the high voltage VPP according to a charge pumping operation when it iS provided with a pumping clock Signal CLK_VPP. The high voltage generator 130 iS illuStrated in FIG. 2 in detail.
Referring to FIG. 2, the high voltage generator 130 includeS a voltage pumping unit 210, a pumping clock controller 220, and a voltage trimming controller 230. The voltage pumping unit 210 performs a charge pumping operation in reSponSe to the pumping clock Signal CLK_VPP to generate the high voltage VPP.
The pumping clock controller 220 includesS a comparator 222 and a NAND gate 224. The comparator 222 receiveS a firSt voltage VPP1 dropped from the high voltage VPP by a voltage acroSS a firSt reSiStor Ra through itS non-inverting port and receiveS a reference voltage Vref through itS inverting port to compare the firSt voltage VPP1 to the reference voltage Vref. The comparator 222 generateS a logic high level sSignal when the firSt voltage VPP1 iS lower than the reference voltage Vref and generatesS a logic low level Signal when the firSt voltage iS higher than the reference voltage Vref. The NAND gate 224 receiveS a clock Signal OSC, a control Signal Control and the output Signal of the comparator 222 and generateS the pumping clock Signal CLK_VPP. The control Signal Control inStructS the high voltage VPP to be generated.
ThuS, the pumping clock controller 220 generateS the pumping clock Signal CLK_VPP in reSponSe to the clock Signal OSC when the control Signal Control and the output Signal of the comparator 222 have a logic high level. When any one of the control Signal Control and the output Signal of the comparator 22 haS a logic low level, the pumping clock controller 220 doeS not generate the pumping clock Signal CLK_VPP.
The voltage trimming controller 230 includeS firSt, Second and third reSiStorS Ra, Rb and Rc, a firSt reSiStor trimming part 232, and a Second reSiStor trimming part 234. The firSt reSiStor Ra iS connected between the high voltage VPP and the firSt voltage VPP1 and the Second reSiStor Rb iS connected between the firSt voltage VPP1 and a Second voltage VPP2 that iS the output of the firSt reSiStor trimming part 232. The third reSiStor Rc iS connected between the firSt voltage VPP1 and a third voltage VPP3 that iS the output of the Second reSiStor trimming part 234.
The firSt reSiStor trimming part 232 iS connected between the Second voltage VPP2 and a ground voltage VSS and includeS a plurality of reSiStorS R1, R2 and R3 and a plurality of tranSiStorS M1, M2 and M3. The reSiStorS R1, R2 and R3 are Serially connected to the tranSiStorS M1, M2 and M3, reSpectively. The gateS of the tranSiStorS M1, M2 and M3 reSpectively receive firSt trimming SignalS VPP_Set1<2:0>. The level of the Second voltage VPP2 iS varied by the tranSiStorS M1, M2 and M3 Selectively turned on in reSponSe to the firSt trimming SignalS VPP_Set1<2:0>.
The Second reSiStor trimming part 234 iS connected between the third voltage VPP3 and the ground voltage VSS and includeS a plurality of reSiStorS R4, R5 and R6 and a plurality of transistors M4, M5 and M6. The resistors R4, R5 and R6 are serially connected to the transistors M4, M5 and M6, respectively. The gates of the transistors M4, M5 and M6 respectively receive second trimming signals VPP_Set2<2:0>. The level of the third voltage VPP3 iS varied by the transistors M4, M5 and M6 selectively turned on in response to the second trimming signals VPP_set2<2:0>.
As a result, in the voltage trimming controller 230, the voltage across the second reSiStor Rb and the second voltage VPP2 of the firSt resistor trimming part 232 are connected in parallel with the voltage across the third resistor Rc and the third voltage VPP3 of the Second resistor trimming part 234 to generate the firSt voltage VPP1, and the firSt voltage VPP1 iS increaSed by the voltage across the firSt resistor Ra to generate the high voltage VPP. Here, the level of the high voltage VPP is varied in response to the first trimming Signals VPP_Set1<2:0> and the Second trimming SignalS VPP_set2<2:0>.
The high voltage VPP generated by the high voltage generator 130 is provided to the block wordline BLKWL of FIG. 1. In the flash memory device 100 of FIG. 1, the program voltage Vpgm may be applied to a wordline enabled in a programming operation, for example, the firSt wordline WL0. The pass voltage Vpass may be applied to the other wordlineS WL1 through WL15. To apply the program voltage Vpgm provided by the decoder 122 to the first wordline WL0, the program voltage Vpgm is applied to the wordline signal so and the high voltage VPP is provided to the block wordline BLK to turn on the pass tranSiStor WN0.
Here, the program voltage Vpgm is increased according to the number of programming times to reach approximately 15 through 20V. The high voltage VPP has a level ranging from at least the level of the program voltage to a voltage level as high as the threshold voltage Vetch of the pass transistor WN0 in order to transfer the program voltage Vpgm without having a voltage drop. However, the high voltage VPP generated by the high voltage generator 130 has a Sufficiently high voltage, for example, 22 through 25V, irrespective of the level of the program voltage Vpgm. The high voltage VPP has a fixed level determined by adding the threshold voltage Vth of the high voltage pass transistors SN0, WL0 through WL15, GN and CN to the maximum program voltage Vpgm.
However, the threshold voltage Vth of the pass transistors SN0, WL0 through WL15, GN and CN may vary within a semiconductor fabrication process. As a result, the high voltage generator 130 requires a trimming operation that Selectively activates the first and Second trimming Signals VPP_Set1<2:0> and VPP_Set2<2:0> to control the level of the high voltage VPP.
In practice, an appropriate voltage level of the block wordline BLKWL for transferring the program voltage Vpgm to the worldliness WL0 through WL15 when the flash memory device performs the programming operation is the program voltage Vpgm plus the threshold voltage Vth of the high voltage pass transistors SN0, WL0 through WL15, GN and CN. However, the high voltage generator 130 causes unnecessary power consumption because it generates the high voltage VPP fixed to a sufficiently high voltage level irrespective of the level of the program voltage Vpgm. Furthermore, the high voltage generator 130 requires the trimming operation using the first and Second trimming Signals VPP_set1<2:0> and VPP_set2<2:0> in order to change the fixed level of the high voltage VPP.
Accordingly, there is a need for a high voltage generator capable of providing a high voltage as high as the current program voltage plus the threshold voltage of the high voltage pass transistors SN0, WL0 through WL15, GN and CN in the event of the programming operation.